1. Field of the Invention
The invention relates to the field of semiconductor, more particularly, to a preparation process of image sensors.
2. Description of the Related Art
CMOS image sensors belong to photoelectric components, CMOS image sensors gradually become the mainstream of the image sensor because of its manufacturing process compatible with integrated circuit fabrication process, and its performance has many advantages over the original charge-coupled device (CCD) image sensor. CMOS image sensors can integrate drive circuit and pixel together, which simplifies hardware design and reduces system power consumption. CMOS image sensors can also process image information in time due to it can remove the electrical signals while acquiring the optical signals, its speed is faster than a CCD image sensor, at the same time CMOS image sensors also have the advantages of cheap, large bandwidth, anti-blur, the flexibility of access and large filling coefficient, and get a lot of use, and are widely used in industrial automation and consumer electronics and other products, such as monitors, video communications and toys. Given the many advantages of CMOS image sensors, research and development of CIS now is to achieve versatility and intelligence using its system integration advantages, and achieve high frame rate CMOS through reading only a small interest area of photosensitive surface using its advantages of accessing flexibly, while the wide dynamic range, high resolution and low noise technology of CMOS image sensors is also in constant development.
The preparation process of image sensors in the current technology is shown in FIG. 1a˜1b, firstly providing a semiconductor structure comprising first wafer 1 and second wafer 2, the first wafer comprises a substrate 1a and an oxide layer 1b, similarly the second wafer 2 comprises a substrate 2a and an oxide layer 2b; In addition, a groove is set in the top of the second wafer 2, and an electrode 4 is set in the groove, and the top of the substrate 2a and the exposed surface of the groove are covered with first electricity layer 3, its structure is shown in FIG. 1; then depositing a thicker second dielectric layer 5 covering the first dielectric layer 3 and filling the remaining portion of the groove, as shown in FIG. 2, and then flattening processing the second dielectric layer 5. However, those skilled in the field discover that after the flattening processing of the second dielectric layer 5, the thickness of the rest of the second dielectric layer 5 in different positions varies considerably. This is because the dielectric layer at the top of the groove will correspondingly form notches while depositing the second dielectric layer 5, so during the grinding, the grinding rate of the second dielectric layer 5 near the notches in general will be greater than the grinding rate of other locations, and then it is easy to produce dishing 6. Those skilled in the field don't expect to see the above problems.